SoC ASIC/FPGA Design Engineer (RTL, C/C++, Python)
|
Edison Smart
Kings Langley
A leading technology firm in the United Kingdom is seeking an ASIC Hardware Engineer with a strong background in ASIC and FPGA design. The ideal candidate will have experience in RTL design at the SoC level and programming skills in C/C++ and Python. This is a great opportunity to advance your career in a company that delivers advanced semiconductor IP across various devices. If you're... |
View salary & More Info |
|
9 hours ago
|
|